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The DLO4135/DLG4137 5 x 7 Dot Matrix Intelligent Display(R) Appnote 28
This application note is intended to serve as a design and application guide for users of the DLO4135 and DLG4137 OSRAM Intelligent Displays. This appnote covers device electrical description, operation, general circuit design considerations, and interfacing to microprocessors. Electrical Description The DLO4135/DLG4137 Intelligent Alphanumeric 5x7 Dot Matrix Display contains memory, character generator, multiplexing circuits, and drivers built into a single package. Figure 1 is a block diagram of DLO4135/DLG4137. The unit consists of 35 LED die arranged in a 5x7 pattern and a single CMOS integrated circuit chip. The IC chip contains the column drivers, row drivers, 128 character generator ROM, memory, multiplex and blanking circuitry. Figure 1. DLO4135/DLG4137 block diagram
Device marking begins over pin 1 .14 min. (3.56) .100 (2.54) .310 (7.87) .100 (2.54) .235 (5.97) .43 (10.92) 1.00 max. (25.4) .065 typ. (.165) DLO4135 Z D0 D1 Memory D2 D3 D4 D5 D6 Character ROM ROW Driver .100 (2.54) .300 (7.62) .012 (.30) .043 (1.09) .500 max. (12.7) .30 (7.62)
for industrial control applications. Display construction is filled reflector type with the integrated circuit in the back also filled with IC-grade epoxy. This results in a very rugged part which is resistant to moisture, shock and vibration. Figure 2. Physical dimensions in inches (mm)
v SIEMENS YYWW
DLO 4135
0.18 .02 (4.57) (.51) .100 (2.54) typ. EIA date code Luminous intensity code
.310 (7.87)
Table 1. DLO4135/DLG4137 pin functions Pin 1 Function LT Lamp Test WR Write BL1 Brightness BL0 Brightness No Pin No Pin CE Chip Enable GND Pin 9 10 11 12 13 14 15 16 Function D0 data LSB D1 data D2 data D3 data D4 data D5 data D6 data MSB +VCC
Z
WR CE Multiplex Circuitry Column Driver
2 3 4 5
BL0 BL1 LT
6 7 8
Thirty-five dots form a 0.30 x 0.43 inch overall character size in a.500 x 1.00 inch dual-in-line package. The 50 degree wide viewing angle complements the display and is the ideal display
2000 Infineon Technologies Corp. * Optoelectronics Division * San Jose, CA www.infineon.com/opto * 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG * Regensburg, Germany www.osram-os.com * +49-941-202-7178
1
May 31, 2000-13
Table 2. Pin description VCC GND D0-D6 CE Positive Supply +5 volts Ground Data Lines, see Figure 3 (Character set) Chip Enable (active low) This determines which device in an array will accept data Write (active low) Data and chip enable must be present and stable before and after the write pulse (see data sheet for timing) Blanking Control Input (active low) Used to control the level of display brightness Lamp Test (active low) Causes all dots to light at 12 brightness
Figure 4. Timing characteristics
WR TW CE TCES
TDH D0 - D6 TDS
WR
BL0, BL1 LT
Display Blanking and Dimming The DLO4135/DLG4137 Intelligent Display has the capability of three levels of brightness plus blank. Figure 5 shows the combination of BL0 and BL1 for the different levels of brightness. The BL0 and BL1 inputs are independent of write and chip enable and does not affect the contents of the internal memory. A flashing display can be achieved by pulsing the blanking pins at a 1-2 hertz rate. Either BL0 or BL1 should be held high to light up the display. Table 3. Dimming and blanking control Brightness Level Blank 1/ 7 brightness 1/ 2 brightness full brightness Lamp Test The lamp test when activated causes all dots on the display to be illuminated at 1/7 brightness. It does not destroy any previously stored characters. The lamp test function is independent of chip enable, write, and the settings of the blanking inputs. This convenient test gives a visual indication that all dots are functioning properly. The lamp test can be used as a cursor or pointer in a line of displays because it does not affect the display memory. General Design Considerations When using the DLO4135/DLG4137 on a separate display board having more than 6 inches of cable length, it may be necessary to buffer all of the input lines. A non-inverting 74LS244 buffer can be used. The object is to prevent current transient into the DLO4135/DLG4137 protection diodes. The buffers should be located on the display board and as close to the displays as possible. Because of high switching currents caused by the multiplexing, local power supply by-pass-capacitors are also needed in many cases. These should be 10 voIt, tantalum type having 10 uf capacitance. The capacitors may only be required every 2 displays depending on the line regulation and other noise generators. Decoupling capacitors should also be used across VCC and ground of each display. Typical value of these capacitors is 0.01 mF/ 10 V. BL1 0 0 1 1 BL0 0 1 0 1
Operation In a dot matrix display system, it is advantageous to use a multiplexed approach with 12 drivers (5 digit plus 7 segments) rather than 35 segment drivers. This obviously reduces the number of drivers and interconnections required. A multiplexed system must be a synchronous system, or the digits or elements may have different on (lit) times and therefore varying brightness. The DLO4135/DLG4137 is an internally multiplexed display, but the data entry is asynchronous. Loading data is similar to writing into a RAM. Present the data, select the chip, and give a write signal. For a multi digit system, each digit has its own unique address location and will display its contents until replaced by another code. The waveforms of Figure 4 shows the relationship of the signals required to generate a write cycle. Check the data sheet for minimum values required for each signal. Figure 3. Character set
D0 D1 D2 D3 D6 D5 D4 HEX ASCII CODE 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 2 1 1 0 0 3 0 0 1 0 4 1 0 1 0 5 0 1 1 0 6 1 1 1 0 7 0 0 0 1 8 1 0 0 1 9 0 1 0 1 A 1 1 0 1 B 0 0 1 1 C 1 0 1 1 D 0 1 1 1 E 1 1 1 1 F
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
1. High=1 level. 2. Low=0 level.
2000 Infineon Technologies Corp. * Optoelectronics Division * San Jose, CA www.infineon.com/opto * 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG * Regensburg, Germany www.osram-os.com * +49-941-202-7178
Appnote 28
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May 31, 2000-13
If small wire cables are used, good engineering practice is to calculate the wire resistance of the ground and the +5 volt wires. More than 0.2 volt drop (at 100 ma per digit) should be avoided, since this loss is in addition to any inaccuracies or load regulation of the power supply. The 5 volt power supply for the DLO4135/DLG4137 should be the same one supplying the VCC to all logic devices. If a separate power supply must be used, then local buffers should be used on all the inputs. These buffers should be powered from the display power supply. This precaution is to avoid line transients or any logic signals to be higher than VCC during power up. Figure 5. Block diagram of the Intel 8031 controller
DO
x x x x x
Subroutine to Load an 8-digit Display using the DLO4135/ DLG4137
; DATA IN RAM 10H-17H (MSD-LSD) ; PORT 1 ALL HIGH (WRITE) ; PORT 2 ALL LOW (DATA) ; RAM ADDRESS--1 ; WRITE PULSE ; COUNTER ; INCREMENT RAM POINTER ; FETCH DATA FROM RAM ; LOAD PORT 2 ; RECALL WRITE ; SHIFT A TO NEXT WRITE ; SAVE WRITE ; SEND WRITE PULSE ; WAIT ; RESET WRITE PULSE ; LOAD COMPLETE? ; RETURN TO MAIN PROGRAM
INIT
D7
BUFFER
P3.0 P3.1 P3.2 P3.6
ORL ORL MOV MOV MOV START: INC DATA: MOV OUTL MOV RR MOV WRITE: OUTL MOV OUTL DJNZ RET
P1,#0FFH P2,#00H R1,#OFH R2,#0FEH R3,#08H R1 A,@R1 P2,A A,R2 A R2,A P1,A A,#OFFH P1,A R3,START
BLO BL1 LT WR CE
74LS244
BLO BL1 LT WR CE
8031
PO
8
Figure 7. Block diagram for 8-digit DLO4135/DLG4137
74LS138
8 3
8 ALE PSEN
74373
Eight DLX413X 8080 or 8085 System Data I/OW Decoder A0 A1 Address A2
8 A0-A7
LATCH
OE
DECODER
EPROM 27xx
Interfacing For an eight digit display using the DLO4135/DLG4137, interfacing to a single chip microprocessor such as the 8748, is easy and straight forward. One approach may be to dedicate one port for the seven data signals and another 8-bit port for the write signals. The schematic is shown in Figure 6. I/O or Memory Mapped System For a memory mapped system using a processor such as the 8080 or 8085, the interfacing is also straight-forward. Each display is treated as a memory location with its own address, like another I/O or RAM location. See Figure 7. Figure 6. DLO4135/DLG4137 with 8748 Routine for an 8-Digit Display using the DLO4135/DLG4137 and 8085 or 8080 Microprocessor
; ; ; ; ; ; ; ; ; ; DATA TO BE DISPLAYED IS IN A0 (LSD) THRU A7 (MSD) DISPLAY ADDRESS C00X LSD IS RIGHT MOST DIGIT DOES NOT SAVE REG A,B,H,L,D,E
DADD EQU DPAD EQU LEN EQU 100H
0A000H 0C000H 08H
P2
6543210
7 D0 D1 D2 D3 D4 D5 D6
8748 6
DATA ADDRESS LOCATION DISPLAY ADDRESS LOCATION ; DISPLAY LENGTH ; ; ; ; ; ; ; ; ; ; ; ; ; ; LOAD DATA ADDRESS LOAD DISPLAY ADDRESS LOAD DISPLAY LENGTH GET DATA XCHG H/L & D/E LOAD DISPLAY FROM REG A RESTORE H/L & D/E INCREMENT DISPLAY ADDRESS INCREMENT DATA ADDRESS DECREMENT LENGTH COUNTER END OF DISPLAY? RETURN TO MAIN PROGRAM
Appnote 28
P1 5 4 3 2 1 0
ORG DISP:
DLO 4135 DLG 4137
+
LXI LXI MVI DISP1: MOV XCHG MOV XCHG INX INX DCR JNZ RET
(MSD)
(LSD)
H,DADD D,DPAD B,LEN A,M M,A D H B DISP1
2000 Infineon Technologies Corp. * Optoelectronics Division * San Jose, CA www.infineon.com/opto * 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG * Regensburg, Germany www.osram-os.com * +49-941-202-7178
B0 B1 LT B0 B1 LT B0 B1 LT B0 B1 LT B0 B1 LT B0 B1 LT B0 B1 LT B0 B1 LT
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May 31, 2000-13
Conclusion Note that although other manufacturers' products are used in the examples, this application note does not imply specific endorsement, or warranty of other manufacturer's products by OSRAM. The interface schemes shown demonstrate the simplicity of using the DLO4135/DLG4137 dot matrix Intelligent DisProgram Listing
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
play. Slight timing differences may be encountered for various microprocessors, but can be resolved using similar methods as those used when using interfacing microprocessors with various RAMs. The techniques used in the examples were shown for their generality. The user will undoubtedly invent other schemes to optimize his particular system to its requirements.
; BY DAN WATSON ; TO DO LAMP TEST, SET 100% BRIGHTNESS ; AND WRITE `SIEMENS*' ; P3.0 = BLO\ ; P3.1 = BL1\ ; P3.2 = LT\ ; P3.6 = WR\ ; RO = DIGIT ADDRESS ( CHIP ENABLES - CE\ ) ; R1 = DIGIT COUNTER ; R7 = R6 = R5 = WAIT REGISTERS 0000 0000 0003 0006 0009 000C 000F 0010 0011 0013 0015 0017 001A 001B 001C 001D 001E 001F 0021 0022 0024 0024 0024 0026 0027 0029 002A 002C 002D 002F 0030 0032 0033 0035 0036 0037 003C 003F 003F .ORG 00H INIT:JMP BEGIN BEGIN:CALL WAIT1 MOV P3,#00H CALL WAIT1 MOV P3,#07H NOP NOP MOV R0,#00H MOV R1,#08H MOV A,#00H MOV DPTR,#TEXT WRT:MOVC A,@A+DPTR MOVX @R0,A INC DPTR INC R0 CLR A DJNZ R1,WRT GO:NOP JMP GO
02 12 75 12 75 00 00 78 79 74 90 93 F2 A3 08 E4 D9 00 01
00 00 B0 00 B0
03 24 00 24 07
; ; ; ;
DELAY FOR uC TO STABILIZE LAMP TEST DISPLAY LT\ FOR A WHILE SET ALL 8 DISPLAYS TO 100% BRT
00 08 00 00 37
; ; ; ; ; ; ; ;
DIGIT 7 ADDRESS 8 DIGIT COUNTER CLEAR ACC. ADDRESS OF THE MESSAGE LOAD FIRST CHAR. INTO THE ACC. DIGIT ADDRESS AND DATA WRITE NEXT CHARACTER ADDRESS NEXT DIGIT (6) ADDRESS
F9 21
; WRITE ALL 8 CHAR. ; MESSAGE ALWAYS ON
7F 88 00 7E FF 00 7D FF 00 DD FE 00 DE F8 00 DF F2 00 22 53 49 45 4D 45 4E 53 2A .END
WAIT1:MOV R7,#88H NOP WAIT2:MOV R6,#FFH NOP WAIT3:MOV R5,#FFH NOP DJNZ R5,$ NOP DJNZ R6,WAIT3 NOP DJNZ R7,WAIT2 NOP RET TEXT:DB `SIEMENS*'
; DELAY LOOPS
2000 Infineon Technologies Corp. * Optoelectronics Division * San Jose, CA www.infineon.com/opto * 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG * Regensburg, Germany www.osram-os.com * +49-941-202-7178
Appnote 28
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May 31, 2000-13

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